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1 block diagram features description 16-bit, 210msps high performance adc the lt c ? 2107 is a 16-bit, 210msps high performance adc. the combination of high sample rate, low noise and high linearity enable a new generation of digital radio designs . the direct sampling front-end is designed specifically for the most demanding receiver applications such as software defined radio and multi-channel gsm base stations. the ac performance includes, snr = 80 dbfs, sfdr = 98dbfs. aperture jitter = 45 fs rms allows direct sampling of if frequencies up to 500mhz with excellent performance . features such as internal dither, a pga front-end and digital output randomization help maximize performance. modes of operation can be controlled through a 3-wire serial interface (spi). the double data rate ( ddr) low voltage differential ( lvds) digital outputs help reduce digital line count and enable space saving designs. 128k point fft , f in = 30.6mhz, C1dbfs, pga = 0 applications n 98dbfs sfdr n 80dbfs snr noise floor n aperture jitter = 45fs rms n pga front-end 2.4v p-p or 1.6v p-p input range n optional internal dither n optional data output randomizer n power dissipation: 1280mw n shutdown mode n serial spi port for configuration n clock duty cycle stabilizer n 48-lead (7mm 7mm) qfn package n software defined radios n military radio and radar n cellular base stations n spectral analysis n imaging systems n ate and instrumentation ? + 16-bit adc core input s/h analog input correction logic output buffers 16 clkout ognd 2107 bd d14_15 d0_1 1f 10f 2.5v 1.8v enc + enc ? a in ? a in + v cm v cm sense 0v gnd of ov dd clock and clock control internal reference v cm driver ser/ par sdi sck cs sdo shdn adc control/spi interface 2.2f v dd l, lt , lt c , lt m , linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 7683695, 8482442, 8648741. frequency (mhz) 0 15 30 45 60 75 90 ?140 amplitude (dbfs) ?120 ?100 ?80 0 ?40 ?20 ?60 ?130 ?110 ?90 ?10 ?50 ?30 ?70 105 2107 ta01 ltc 2107 2107f for more information www.linear.com/ltc2107
2 pin configuration absolute maximum ratings supply voltage v dd ...................................................... C0. 3 v to 2.8 v ov dd ........................................................ C0. 3 v to 2v analog input voltage a in + , a in C , enc + , enc C , par / ser , sense ( no te 3) ................................... C 0.3 v to (v dd + 0.2 v) digital input voltage cs , sdi , sck ( note 4) ........................... C 0.3 v to 3.9 v (notes 1, 2) order information full-rate cmos output mode top view 49 gnd uk package 48-lead (7mm 7mm) plastic qfn sense 1 gnd 2 gnd 3 v dd 4 v dd 5 v dd 6 gnd 7 a in + 8 a in ? 9 gnd 10 v cm 11 gnd 12 36 d13 35 d12 34 d11 33 d10 32 clkout + 31 clkout ? 30 d9 29 d8 28 d7 27 d6 26 d5 25 d4 48 gnd 47 gnd 46 par/ ser 45 cs 44 sck 43 sdi 42 ognd 41 ov dd 40 of 39 dnc 38 d15 37 d14 gnd 13 enc + 14 enc ? 15 gnd 16 shdn 17 sdo 18 ognd 19 ov dd 20 d0 21 d1 22 d2 23 d3 24 t jmax = 150c, v ja = 29c/w exposed pad ( pin 49) is gnd, must be soldered to pcb double data rate lvds output mode top view 49 gnd uk package 48-lead (7mm 7mm) plastic qfn sense 1 gnd 2 gnd 3 v dd 4 v dd 5 v dd 6 gnd 7 a in + 8 a in ? 9 gnd 10 v cm 11 gnd 12 36 d12_13 + 35 d12_13 ? 34 d10_11 + 33 d10_11 ? 32 clkout + 31 clkout ? 30 d8_9 + 29 d8_9 ? 28 d6_7 + 27 d6_7 ? 26 d4_5 + 25 d4_5 ? 48 gnd 47 gnd 46 par/ ser 45 cs 44 sck 43 sdi 42 ognd 41 ov dd 40 of + 39 of ? 38 d14_15 + 37 d14_15 ? gnd 13 enc + 14 enc ? 15 gnd 16 shdn 17 sdo 18 ognd 19 ov dd 20 d0_1 ? 21 d0_1 + 22 d2_3 ? 23 d2_3 + 24 t jmax = 150c, v ja = 29c/w exposed pad ( pin 49) is gnd, must be soldered to pcb digital output voltage ................ C 0.3 v to ( ov dd + 0.3 v) sdo ( no te 4) ........................................ C 0.3 v to 3.9 v operating temperature range ltc 2 107 c ................................................ 0 c to 70 c ltc 2 107 i.............................................. C40 c to 85 c storage temperature range .................. C 65 c to 150 c lead free finish tape and reel part marking* package description temperature range ltc2107cuk#pbf ltc2107cuk#trpbf ltc2107uk 48-lead (7mm w 7mm) plastic qfn 0c to 70c ltc2107iuk#pbf ltc2107iuk#trpbf ltc2107uk 48-lead (7mm w 7mm) plastic qfn C40c to 85c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ ltc 2107 2107f for more information www.linear.com/ltc2107
3 converter characteristics analog input the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) parameter conditions min typ max units resolution (no missing codes) l 16 bits integral linearity error differential analog input (note 6) l C4.5 1.6 4.5 lsb differential linearity error differential analog input C1 0.4 1.0 lsb offset error (note 7) l C5 C0.5 5 mv gain error internal reference, pga = 0 external reference, pga = 0 l C0.85 1.5 C0.2 0.85 % fs %fs offset drift C20 v/c full-scale drift internal reference, pga = 0 external reference, pga = 0 110 70 ppm /c ppm/c transition noise external reference, pga = 0 external reference, pga = 1 2.3 3.0 lsb rms lsb rms noise density, input referred pga = 0, sample rate = 210msps, bandwidth = 105mhz pga = 1, sample rate = 210msps, bandwidth = 105mhz 8.3 7.2 nv / hz nv/hz symbol parameter conditions min typ max units v in analog input range (a in + C a in C ) 2.375v < v dd < 2.625v, pga = 0 2.375v < v dd < 2.625v, pga = 1 l l 2.4 1.6 v p-p v p-p v in(cm) analog input common mode (a in + + a in C )/2 differential analog input (note 8) l 1.15 v cm 1.25 v v sense external voltage reference applied to sense external reference mode l 1.225 1.250 1.275 v i in1 analog input leakage current 0.6v < a in + < 1.8v, 0.6v < a in C < 1.8v l C1 1 a i in2 sense, par /ser input leakage current 0 < sense, par /ser < v dd l C1 1 a t ap sample-and-hold acquisition delay time r s = 25 0.5 ns t jitter sample-and-hold acquisition delay jitter (note 11) 45 fs rms bw-3db full-power bandwidth r s = 25 800 mhz over-range recovery time 120% full scale (note 10) 1 cycles ltc 2107 2107f for more information www.linear.com/ltc2107
4 dynamic accuracy the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. a in = C1dbfs. (note 5) symbol parameter conditions min typ max units snr signal-to-noise ratio 5.1mhz input (pga = 0) 30.3mhz input (pga = 0) 71.1mhz input (pga = 0) 141mhz input (pga = 0) l 78 79.8 79.7 79.5 79.1 dbfs dbfs dbfs dbfs 141 mhz input (pga = 1) 250mhz input (pga = 0) 250mhz input (pga = 1) l 75.2 77.0 78.2 76.4 dbfs dbfs dbfs sfdr spurious free dynamic range 2nd harmonic 5.1mhz input (pga = 0) 30.3mhz input (pga = 0) 71.1mhz input (pga = 0) 141mhz input (pga = 0) l 84 104.3 96.8 87 87.5 dbfs dbfs dbfs dbfs 141 mhz input (pga = 1) 250mhz input (pga = 0) 250mhz input (pga = 1) l 84 95.5 85.8 89.3 dbfs dbfs dbfs spurious free dynamic range 3rd harmonic 5.1mhz input (pga = 0) 30.3mhz input (pga = 0) 71.1mhz input (pga = 0) 141mhz input (pga = 0) l 86 98 96.8 87 93.3 dbfs dbfs dbfs dbfs 141 mhz input (pga = 1) 250mhz input (pga = 0) 250mhz input (pga = 1) l 86 100 80.4 83.5 dbfs dbfs dbfs spurious free dynamic range 4th harmonic or higher 5.1mhz input (pga = 0) 30.3mhz input (pga = 0) 71.1mhz input (pga = 0) 141mhz input (pga = 0) l 93 100.8 101.6 100.7 105 dbfs dbfs dbfs dbfs 141 mhz input (pga = 1) 250mhz input (pga = 0) 250mhz input (pga = 1) l 91 96.4 95.7 96.3 dbfs dbfs dbfs s /(n+d) signal-to-noise plus distortion ratio 5.1 mhz input (pga = 0) 30.3mhz input (pga = 0) 71.1mhz input (pga = 0) 141mhz input (pga = 0) l 77 79.4 79.5 78.4 78.7 dbfs dbfs dbfs dbfs 141 mhz input (pga = 1) 250mhz input (pga = 0) 250mhz input (pga = 1) l 74 76.7 76.7 76.0 dbfs dbfs dbfs sfdr spurious free dynamic range at C25dbfs dither "off" 5.1mhz input (pga = 0) 30.3mhz input (pga = 0) 71.1mhz input (pga = 0) 141mhz input (pga = 0) l 95 100.4 107.4 106.6 108.3 dbfs dbfs dbfs dbfs 141 mhz input (pga = 1) 250mhz input (pga = 0) 250mhz input (pga = 1) 106.7 106.7 106.7 dbfs dbfs dbfs spurious free dynamic range at C25dbfs dither "on" 5.1mhz input (pga = 0) 30.3mhz input (pga = 0) 71.1mhz input (pga = 0) 141mhz input (pga = 0) l 103 126 124 119 119 dbfs dbfs dbfs dbfs 141 mhz input (pga = 1) 250mhz input (pga = 0) 250mhz input (pga = 1) 122.3 124.4 124.6 dbfs dbfs dbfs snrd snr density sample rate = 210msps, pga = 0 sample rate = 210msps, pga = 1 160.2 157.9 dbfs/ hz dbfs/hz ltc 2107 2107f for more information www.linear.com/ltc2107
5 v cm output digital inputs and outputs the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) parameter conditions min typ max units v cm output voltage i out = 0 1.17 1.20 1.23 v v cm output temperature drift 18 ppm/c v cm output resistance C1ma < i out < 1ma 0.35 v cm line regulation 2.375v < v dd < 2.625v 0.8 mv/v symbol parameter conditions min typ max units encode inputs (enc + , enc C ) v id differential input voltage (note 8) l 0.2 2 v v icm common mode input voltage internally set externally set (note 8) 1.1 1.2 1.5 v v v in input voltage range enc + , enc C to gnd l 0 2.5 v r in input resistance (see figure 8) 5 k r term optional encode termination encode termination enabled (see figure 8) 107 c in input capacitance between enc + and enc C (note 8) 3 pf digital inputs (cs, sdi, sck, shdn) v ih high level input voltage v dd = 2.5v l 1.2 v v il low level input voltage v dd = 2.5v l 0.6 v i in input current v in = 0v to 3.6v l C10 10 a c in input capacitance (note 8) 2 pf sdo output (open-drain output. requires 2k pull-up resistor if sdo is used) r ol logic low output resistance to gnd v dd = 2.5v, sdo = 0v 260 i oh logic high output leakage current sdo = 0v to 3.6v l C10 10 a c out output capacitance (note 8) 2 pf digital data outputs (cmos mode) v oh high level output voltage i o = C500a l 1.7 1.790 v v ol low level output voltage i o = 500a l 0.010 0.050 v digital data outputs (lvds mode) v od differential output voltage 100 differential load, 3.5ma mode 100 differential load, 1.75ma mode l l 247 125 350 175 454 250 mv mv v os common mode output voltage 100 differential load, 3.5ma mode 100 differential load, 1.75ma mode l l 1.19 1.20 1.250 1.250 1.375 1.375 v v r term on-chip termination resistance termination enabled, ov dd = 1.8v, 3.5ma mode 100 ltc 2107 2107f for more information www.linear.com/ltc2107
6 power requirements timing characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 9) the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) symbol parameter conditions min typ max units v dd analog supply voltage (note 9) l 2.375 2.5 2.625 v ov dd output supply voltage cmos mode (note 9) lvds mode (note 9) l l 1.7 1.7 1.8 1.8 1.9 1.9 v v i vdd analog supply current l 495.3 545 ma i ovdd digital supply current cmos mode lvds mode, 1.75ma mode lvds mode, 3.5ma mode l l 61 23.2 45 26 50 ma ma ma p diss power dissipation cmos mode lvds mode, 1.75ma mode lvds mode, 3.5ma mode l l 1348 1280 1320 1409 1453 mw mw mw p shdn shdn mode power 6.4 mw i vdd analog supply current with inactive encode encode clock not active keep alive oscillator enabled 366 ma symbol parameter conditions min typ max units f s sampling frequency (note 9) l 10 210 mhz t l enc low time duty cycle stabilizer off (note 8) duty cycle stabilizer on (note 8) l l 2.26 1.16 2.38 2.38 50 50 ns ns t h enc high time duty cycle stabilizer off (note 8) duty cycle stabilizer on (note 8) l l 2.26 1.16 2.38 2.38 50 50 ns ns t ap sample-and-hold acquisition delay time r s = 25 0.5 ns digital data outputs (cmos mode) t d enc to data delay c l = 6.8pf (notes 8, 12) l 1.3 1.9 2.5 ns t c enc to clkout delay c l = 6.8pf (notes 8, 12) l 1.3 1.9 2.5 ns t skew data to clkout skew t d C t c (note 8) l C0.3 0 0.3 ns pipeline latency 7 cycles digital data outputs (lvds mode) t d enc to data delay c l = 6.8pf (notes 8, 12) l 1.3 1.9 2.5 ns t c enc to clkout delay c l = 6.8pf (notes 8, 12) l 1.3 1.9 2.5 ns t skew data to clkout skew t d C t c (note 8) l C0.3 0 0.3 ns pipeline latency 7 cycles spi port timing (note 8) t sck sck period write mode (note 8) read back mode, c sdo = 20pf, r pullup = 2k l l 40 250 ns ns t s cs to sck setup time l 5 ns t hs sck to cs setup time l 5 ns t ds sdi setup time l 5 ns t dh sdi hold time l 5 ns t do sck falling to sdo valid read back mode, c sdo = 20pf, r pullup = 2k l 125 ns ltc 2107 2107f for more information www.linear.com/ltc2107
7 electrical characteristics timing diagrams note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to gnd and ognd shorted (unless otherwise noted). note 3: when these pin voltages are taken below gnd or above v dd , they will be clamped by internal diodes. this product can handle input currents of greater than 100ma below gnd or above v dd without latchup. note 4: when these pin voltages are taken below gnd they will be clamped by internal diodes. when these pin voltages are taken above v dd they will not be clamped by internal diodes. this product can handle input currents of greater than 100ma below gnd without latchup. note 5: v dd = 2.5v, ov dd = 1.8v, f sample = 210mhz, lvds outputs, differential enc + /enc C = 2v p-p sine wave, input range = 2.4v p-p (pga = 0) with differential drive, unless otherwise noted. note 6: integral nonlinearity is defined as the deviation of a code from a best fit straight line to the transfer curve. the deviation is measured from the center of the quantization band. note 7: offset error is the offset voltage measured from C0.5lsb when the output code flickers between 0000 0000 0000 0000 and 1111 1111 1111 1111 in 2s complement output mode. note 8: guaranteed by design, not subject to test. note 9: recommended operating conditions. note 10: refer to overflow bit section for additional information. note 11: the test circuit of figure 11 is used to verify jitter perfomance. note 12: c l is the external single-ended load capacitance between each output pin and ground. n-7 n-6 n-5 n-4 2107 td01 analog input enc ? enc + d0-d15, of clkout ? clkout + n t h t d n+1 n+2 n+3 n+4 t ap t c t l cmos output timing mode all outputs are single-ended and have cmos levels ltc 2107 2107f for more information www.linear.com/ltc2107
8 timing diagrams d14 n-7 d15 n-7 n-7 n-6 n-5 n-4 2107 td02 n-3 d14 n-6 d15 n-6 d15 n-5 d14 n-4 d15 n-4 d14 n-3 d14 n-5 d0 n-7 analog input enc ? enc + d0_1 + d0_1 ? d14_15 + d14_15 ? of + of ? clkout ? clkout + d1 n-7 d0 n-6 d1 n-6 d1 n-5 d0 n-4 d1 n-4 d0 n-3 d0 n-5 n t h t d n+1 n+2 n+3 n+4 t c t l t ap double data rate lvds output mode timing all outputs are differential and have lvds levels a6 t s t ds a5 a4 a3 a2 a1 a0 xx d7 d6 d5 d4 d3 d2 d1 d0 xx xx xx xx xx xx xx cs sck sdi r/w sdo high impedance high impedance spi port timing (readback mode) spi port timing (write mode) t dh t do t sck t hs a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 2107 td03 cs sck sdi r/w sdo high impedance ltc 2107 2107f for more information www.linear.com/ltc2107
9 typical performance characteristics 128k point fft , f in = 5.0mhz, C1dbfs, pga = 0, dither on 128k point fft , f in = 30.6mhz, C1dbfs, pga = 0, dither on 128k point fft , 30.6mhz, C20dbfs, pga = 0, dither off 128k point fft , 30.6mhz,C20dbfs, pga = 0, dither on 128k point 2-tone fft , 25.1mhz and 30.51mhz, C7dbfs pga = 0, dither on 128k point 2-tone fft , 25.07mhz and 30.5mhz, C20dbfs pga = 0, dither on integral nonlinearity (inl) vs output code differential nonlinearity (dnl) vs output code ac grounded input histogram output code 0 inl error (lsb) 0 1.0 65536 2107 g01 ?1.0 ?2.0 16384 32768 49152 2.0 ?0.5 0.5 ?1.5 1.5 output code 0 dnl error (lsb) 0 0.50 65536 2107 g02 ?1.50 ?2.00 16384 32768 49152 1.00 ?0.25 0.25 ?1.75 0.75 frequency (mhz) 0 15 30 45 60 75 90 ?130 amplitude (dbfs) ?120 ?100 ?90 ?80 ?30 ?20 ?10 0 ?60 2107 g04 ?110 ?50 ?40 ?70 105 frequency (mhz) 0 15 30 45 60 75 90 ?140 amplitude (dbfs) ?120 ?100 ?80 0 ?40 ?20 ?60 ?130 ?110 ?90 ?10 ?50 ?30 ?70 105 2107 g05 frequency (mhz) 0 15 30 45 60 75 90 ?140 amplitude (dbfs) ?120 ?100 ?80 0 ?40 ?20 ?60 ?130 ?110 ?90 ?10 ?50 ?30 ?70 105 2107 g06 frequency (mhz) 0 15 30 45 60 75 90 ?140 amplitude (dbfs) ?120 ?100 ?80 0 ?40 ?20 ?60 ?130 ?110 ?90 ?10 ?50 ?30 ?70 105 2107 g07 frequency (mhz) 0 15 30 45 60 75 90 ?130 amplitude (dbfs) ?120 ?100 ?90 ?80 ?30 ?20 ?10 0 ?60 2107 g08 ?110 ?50 ?40 ?70 105 frequency (mhz) 0 15 30 45 60 75 90 ?130 amplitude (dbfs) ?120 ?100 ?90 ?80 ?30 ?20 ?10 0 ?60 2107 g09 ?110 ?50 ?40 ?70 105 output code 32799 0 count 3333 6667 10000 32809 2107 g03 32819 ltc 2107 2107f for more information www.linear.com/ltc2107
10 typical performance characteristics 128k point fft , f in = 71.1mhz, C10dbfs, pga = 0, dither on 128k point fft , f in = 71.1mhz, C20dbfs, pga = 0, dither on 128k point fft , f in = 71.1mhz, C20dbfs, pga = 1, dither on sfdr vs input level, f in = 71.1mhz, pga = 1, dither off sfdr vs input level, f in = 71.1mhz, pga = 1, dither on 128k point fft , f in = 71.1mhz and 80mhz, C7dbfs, pga = 0, dither on sfdr vs input level, f in = 30.6mhz, pga = 0, dither off sfdr vs input level, f in = 30.6mhz, pga = 0, dither on 128k point fft , f in = 71.1mhz, C1dbfs, pga = 0, dither on input level (dbfs) ?80 sfdr (dbc and dbfs) 60 120 130 140 ?60 ?40 ?30 ?20 2107 g10 40 100 80 50 110 30 90 70 ?70 ?50 ?10 0 dbfs dbc input level (dbfs) ?80 sfdr (dbc and dbfs) 60 120 130 140 ?60 ?40 ?30 ?20 2107 g11 40 100 80 50 110 30 90 70 ?70 ?50 ?10 0 dbfs dbc frequency (mhz) 0 15 30 45 60 75 90 ?130 amplitude (dbfs) ?120 ?100 ?90 ?80 ?30 ?20 ?10 0 ?60 2107 g12 ?110 ?50 ?40 ?70 105 frequency (mhz) 0 15 30 45 60 75 90 ?130 amplitude (dbfs) ?120 ?100 ?90 ?80 ?30 ?20 ?10 0 ?60 2107 g13 ?110 ?50 ?40 ?70 105 frequency (mhz) 0 15 30 45 60 75 90 ?130 amplitude (dbfs) ?120 ?100 ?90 ?80 ?30 ?20 ?10 0 ?60 2107 g14 ?110 ?50 ?40 ?70 105 frequency (mhz) 0 15 30 45 60 75 90 ?130 amplitude (dbfs) ?120 ?100 ?90 ?80 ?30 ?20 ?10 0 ?60 2107 g15 ?110 ?50 ?40 ?70 105 input level (dbfs) ?80 sfdr (dbc and dbfs) 60 120 130 140 ?60 ?40 ?30 ?20 2107 g16 40 100 80 50 110 30 90 70 ?70 ?50 ?10 0 dbfs dbc input level (dbfs) ?80 sfdr (dbc and dbfs) 60 120 130 140 ?60 ?40 ?30 ?20 2107 g17 40 100 80 50 110 30 90 70 ?70 ?50 ?10 0 dbfs dbc frequency (mhz) 0 15 30 45 60 75 90 ?130 amplitude (dbfs) ?120 ?100 ?90 ?80 ?30 ?20 ?10 0 ?60 2107 g18 ?110 ?50 ?40 ?70 105 ltc 2107 2107f for more information www.linear.com/ltc2107
11 typical performance characteristics sfdr vs input level, f in = 141.1mhz, pga = 1, dither off sfdr vs input level, f in = 141.1mhz, pga = 1, dither on 64k point fft , f in = 170.0mhz, C1dbfs, pga = 1, dither on 128k point fft , f in = 250.0mhz, C1dbfs, pga = 1, dither on 128k point fft , f in = 250.0mhz, C10dbfs, pga = 1, dither on 128k point fft , f in = 380.0mhz, C1dbfs, pga = 1, dither on 128k point fft , f in = 71.1mhz and 80mhz, C15dbfs, pga = 0, dither on 64k point fft , f in = 141.1mhz, C1dbfs, pga = 0, dither on 64k point fft , f in = 141.1mhz, C1dbfs, pga = 1, dither on frequency (mhz) 0 15 30 45 60 75 90 ?130 amplitude (dbfs) ?120 ?100 ?90 ?80 ?30 ?20 ?10 0 ?60 2107 g19 ?110 ?50 ?40 ?70 105 frequency (mhz) 0 15 30 45 60 75 90 ?130 amplitude (dbfs) ?120 ?100 ?90 ?80 ?30 ?20 ?10 0 ?60 2107 g20 ?110 ?50 ?40 ?70 105 frequency (mhz) 0 15 30 45 60 75 90 ?130 amplitude (dbfs) ?120 ?100 ?90 ?80 ?30 ?20 ?10 0 ?60 2107 g21 ?110 ?50 ?40 ?70 105 input level (dbfs) ?80 sfdr (dbc and dbfs) 60 120 130 140 ?60 ?40 ?30 ?20 2107 g22 40 100 80 50 110 30 90 70 ?70 ?50 ?10 0 dbfs dbc input level (dbfs) ?80 sfdr (dbc and dbfs) 60 120 130 140 ?60 ?40 ?30 ?20 2107 g23 40 100 80 50 110 30 90 70 ?70 ?50 ?10 0 dbfs dbc frequency (mhz) 0 15 30 45 60 75 90 ?130 amplitude (dbfs) ?120 ?100 ?90 ?80 ?30 ?20 ?10 0 ?60 2107 g24 ?110 ?50 ?40 ?70 105 frequency (mhz) 0 15 30 45 60 75 90 ?130 amplitude (dbfs) ?120 ?100 ?90 ?80 ?30 ?20 ?10 0 ?60 2107 g25 ?110 ?50 ?40 ?70 105 frequency (mhz) 0 15 30 45 60 75 90 ?130 amplitude (dbfs) ?120 ?100 ?90 ?80 ?30 ?20 ?10 0 ?60 2107 g26 ?110 ?50 ?40 ?70 105 frequency (mhz) 0 15 30 45 60 75 90 ?130 amplitude (dbfs) ?120 ?100 ?90 ?80 ?30 ?20 ?10 0 ?60 2107 g27 ?110 ?50 ?40 ?70 105 ltc 2107 2107f for more information www.linear.com/ltc2107
12 typical performance characteristics snr and sfdr vs sample rate, f in = 5mhz, C1dbfs snr vs input frequency snr and sfdr vs supply voltage (v dd ), f in = 5mhz, C1dbfs i vdd vs sample rate, 5mhz sine wave, C1dbfs normalized full scale vs temperature, internal reference, 5 units normalized full scale vs temperature, external reference, 5 units 128k point fft , f in = 380.0mhz, C10dbfs, pga = 1, dither on hd2/hd3 vs input frequency, pga = 0, C1dbfs hd2/hd3 vs input frequency, pga = 1, C1dbfs frequency (mhz) 0 15 30 45 60 75 90 ?130 amplitude (dbfs) ?120 ?100 ?90 ?80 ?30 ?20 ?10 0 ?60 2107 g28 ?110 ?50 ?40 ?70 105 temperature (c) ?40 0.990 normalized full scale 0.995 1.000 1.005 1.010 ?20 0 20 40 2107 g35 60 80 temperature (c) ?40 0.990 normalized full scale 0.995 1.000 1.005 1.010 ?20 0 20 40 2107 g36 60 80 input frequency (mhz) 0 dbfs 100 110 120 200 2107 g29 90 80 70 50 100 150 250 hd3 hd2 input frequency (mhz) 0 dbfs 100 110 120 200 2107 g30 90 80 70 50 100 150 250 hd3 hd2 input frequency (mhz) 1 74 snr (dbfs) 75 76 77 78 79 80 100 200 300 400 2107 g31 500 pga = 0 pga = 1 sample rate (msps) 0 30 60 snr and sfdr (dbfs) 80 70 60 180 110 100 90 90 120 150 210 2107 g32 sfdr snr supply voltage (v dd ) 2.3 snr and sfdr (dbfs) 90 100 2.7 2107 g33 80 70 2.4 2.5 2.6 110 sfdr snr v dd(min) = 2.375v v dd(max) = 2.625v sample rate (msps) 350 i vdd (ma) 400 450 500 0 30 60 90 120 2107 g34 150 180 210 ltc 2107 2107f for more information www.linear.com/ltc2107
13 typical performance characteristics mid-scale settling after starting encode clock with keep-alive on mid-scale settling after starting encode clock with keep-alive off input offset voltage vs temperature, 5 units sfdr vs analog input common mode voltage, C1dbfs mid-scale settling after wake up from shutdown temperature (c) ?50 ?2.0 offset voltage (mv) ?1.5 ?0.5 0 0.5 50 2.5 2107 g37 ?1.0 0 100 1.0 1.5 2.0 time after wake up from shutdown (s) 0 ?1.0 mid-scale error (%) ?0.5 0 0.5 1.0 1.5 2.0 0.5 1.0 2107 g39 time after clock restart (s) 0 mid-scale error (%) 0 0.05 0.10 0.20 2107 g40 ?0.05 ?0.10 ?0.20 0.05 0.10 0.15 ?0.15 0.20 0.15 clock starts here time after clock restart (s) 0 mid-scale error (%) 0 2107 g41 ?0.10 ?0.20 0.4 0.8 0.2 0.6 1.0 0.10 0.20 ?0.05 ?0.15 0.05 0.15 1.2 clock starts here analog input common mode voltage (v) 1.1 sfdr (dbfs) 90 100 1.3 2107 g38 80 70 1.15 1.2 1.25 110 min max f in = 141.1mhz, pga = 1 f in = 5mhz, pga = 0 ltc 2107 2107f for more information www.linear.com/ltc2107
14 pin functions (pins that are the same for all digital output modes) sense (pin 1): reference programming pin. the sense pin voltage selects the use of an internal reference or an external 1.25 v reference. connecting sense to ground or v dd selects the internal reference. connect sense to a 1.25v external reference and the external reference mode is automatically selected. the external reference must be 1.25v 25mv for proper operation. gnd (pins 2, 3, 7, 10, 12, 13, 16, 47, 48, 49): adc power ground. v dd (pins 4, 5, 6): 2.5 v analog power supply. bypass to ground with an 0402 10 f ceramic capacitor and an 0402 0.1f ceramic capacitor as close to these pins as possible. pins 4, 5 and 6 can share these two bypass capacitors. a in + (pin 8): positive differential analog input. a in C (pin 9): negative differential analog input. v cm (pin 11): common mode bias output, nominally equal to 1.2 v. v cm should be used to bias the common mode of the analog inputs. bypass to ground with a 2.2f ceramic capacitor. enc + (pin 14): encode input. conversion starts on the rising edge. enc C (pin 15): encode complement input. conversion starts on the falling edge. shdn (pin 17): power shutdown pin. shdn = 0 v results in normal operation. shdn = 2.5 v results in powered- down analog circuitry and the digital outputs are set in high impedance state. sdo (pin 18): in serial programming mode, ( par /ser = 0v), sdo is the serial interface data output. data on sdo is read back from the mode control registers and can be latched on the falling edge of sck. sdo is an open-drain nmos output that requires an external 2 k pull - up resistor to 1.8 v-3.3v. if readback from the mode control registers is not needed, the pull-up resistor is not necessary and sdo can be left unconnected. ognd (pins 19, 42): output driver ground. ognd and gnd should be tied together with a common ground plane. ov dd (pins 20, 41): 1.8 v output driver supply. bypass each ov dd pin to ground with an 0402 1 f ceramic capaci- tor and an 0402 0.1 f ceramic capacitor. place the bypass capacitors as close to these pins as possible. pins?20 and 41 cannot share these bypass capacitors. sdi (pin 43): in serial programming mode, ( par /ser = 0v), sdi is the serial interface data input. data on sdi is clocked into the mode control registers on the rising edge of sck. in the parallel programming mode ( par /ser = v dd ), sdi becomes the digital output randomization control bit. when sdi is low, digital output randomization is disabled. when sdi is high, digital output randomization is enabled. sdi can be driven with 1.8v to 3.3v logic. sck (pin 44): in serial programming mode , ( par /ser = 0v), sck is the serial interface clock input. in the parallel programming mode ( par /ser = v dd ), sck controls the programmable gain amplifier front-end, pga. sck low selects a front-end gain of 1, input range of 2.4v p-p . high selects a front-end gain of 1.5, input range of 1.6v p-p . sck can be driven with 1.8v to 3.3v logic. cs (pin 45): in serial programming mode, ( par /ser = 0v), cs is the serial interface chip select input. when cs is low, sck is enabled for shifting data on sdi into the mode control registers. in the parallel programming mode ( par /ser = v dd ), cs controls the digital output mode. when cs is low, the full-rate cmos output mode is enabled. when cs is high, the double data rate lvds output mode ( with 3.5 ma output current) is enabled. cs can be driven with 1.8v to 3.3v logic. par /ser (pin 46): programming mode selection pin. connect to ground to enable the serial programming mode. cs , sck, sdi, sdo become a serial interface that control the a/d operating modes. connect to v dd to enable the parallel programming mode where cs , sck, sdi become parallel logic inputs that control a reduced set of the a/d operating modes. par /ser should be connected directly to ground or the v dd of the part and not be driven by a logic signal. ltc 2107 2107f for more information www.linear.com/ltc2107
15 pin functions full-rate cmos output mode all pins below have cmos output levels ( ognd to ov dd ) cmos output mode is only recommended for sample rates up to 100msps. d0-d15 (pins 21-30, 33-38): digital outputs. d15 is the msb. clkout C (pin 31): inverted version of clkout + . clkout + (pin 32): data output clock. the digital outputs normally transition at the same time as the falling edge of clkout + . the phase of clkout + can also be delayed relative to the digital outputs by programming the mode control registers. dnc (pin 39): do not connect this pin. of (pin 40): over/under flow digital output. of is high when an overflow or underflow has occurred. double data rate lvds output mode all pins below have lvds output levels. the output current level is programmable. there is an optional internal 100 termination resistor between the pins of each lvds output pair. d0_1 C /d0_1 + to d14_15 C /d14_15 + (pins 21/22, 23/24, 25/26, 27/28, 29/30, 33/34, 35/36, 37/38): double data rate digital outputs. tw o data bits are multiplexed onto each differential output pair. the even data bits ( d0, d2, d4, d6, d8, d10, d12, d14) appear when clkout + is low. the odd data bits ( d1, d3, d5, d7, d9, d11, d13, d15) appear when clkout + is high. clkout C /clkout + (pins 31/32): data output clock. the digital outputs normally transition at the same time as the falling and rising edges of clkout + . the phase of clkout + can also be delayed relative to the digital outputs by programming the mode control registers. of C /of + (pins 39/40): over/under flow digital output. of + is high when an overflow or underflow has occurred. of C is an inverted version of of + . ltc 2107 2107f for more information www.linear.com/ltc2107
16 block diagram ? + input s/h correction logic and shift register output buffers pipeline adc stage 6 16 clkout ognd 2107 f01 d14_15 d0_1 1.8v a in ? a in + v cm buffer adc reference of ov dd 2.5v v dd gnd enc + enc ? clock and clock control par/ ser sdi sck cs sdo shdn adc control/spi interface pipeline adc stage 5 pipeline adc stage 4 pipeline adc stage 3 pipeline adc stage 2 pipeline adc stage 1 dither signal generator internal voltage reference sense range select pga figure 1. functional block diagram applications information converter operation the ltc2107 is a high performance pipelined 16-bit 210msps a/d converter with a direct sampling pga front- end. as shown in figure 1, the converter has six pipelined adc stages; a sampled input will result in a digitized result seven cycles later ( see the timing diagrams). the analog input is differential for improved common mode noise re - jection, even order harmonic reduction and for maximum input voltage range. the encode input is also differential for common mode noise rejection and for optimal jitter performance. the digital outputs can be cmos or double data rate lvds ( to reduce digital noise in the system.) many additional features can be chosen by programming the mode control registers through a serial spi port. the ltc2107 has two phases of operation, determined by the state of the differential enc + /enc C input pins. for brevity, the text will refer to enc + greater than enc C as enc high and enc + less than enc C as enc low. successive stages process the signal on a different phase over the course of seven clock cycles in order to create a digital representation of the analog input. when enc is low, the analog input is sampled differentially, directly onto the input sample-and-hold ( s/h) capacitors, ltc 2107 2107f for more information www.linear.com/ltc2107
17 applications information a in + l par 0.7nh c par 0.66pf r on 5.6 v dd ltc2107 1.8 c sample 5.72pf a in ? enc + l par 0.7nh c par 0.66pf 5k 5k v dd /2 v dd /2 2107 f02 v dd r on 5.6 v dd 1.8 c sample 5.72pf enc ? figure 2. equivalent input circuit inside the input s/h shown in the block diagram. at the instant the enc transitions from low to high, the voltage on the sample capacitors is held. while enc is high, the held input voltage is buffered by the s/h amplifier which drives the first pipelined adc stage. the first stage acquires the output of the s/h amplifier during the high phase of enc. when enc goes back low, the first stage produces its output which is acquired by the second stage. at the same time, the input s/h goes back to acquiring the next analog input. when enc goes back high again, the second stage produces its output which is acquired by the third stage. the identical process is repeated for the remaining stages 3-5 finally resulting in an output at the output of the 5 th stage which is sent to the 6 th adc stage for final evaluation. results from all stages are digitally delayed such that stage results are aligned with one analog input sample. the delayed results from all stages are then combined in the correction logic and the final result is sent to the output buffers. sample/hold operation figure 2 shows the equivalent circuit for the ltc2107 direct sampling, differential sample/hold circuit. the dif- ferential analog inputs, a in + and a in C are sampled directly on to the sampling capacitors (c sample ) through nmos transistor switches. the capacitors shown attached to each input (c par ) are the summation of all other capacitance associated with each input, for interconnect and device parasitics. during the sample phase, when enc is low, the nmos switches connect the analog inputs to the sampling capaci - tors, such that they charge to, and track the input voltage. the capacitance seen at the input during the sample phase is the sum of c sample and c par or 6.38 pf. when enc transitions from low to high, the nmos switches open, disconnecting the analog inputs from the sampling capaci - tors. the voltage on the sampling capacitors is held and is passed to the adc core for evaluation. the capacitance seen at the input during the hold phase is c par or 0.66 pf. sampling glitch as enc transitions from high to low, the inputs are re- connected to the sampling capacitors to acquire a new sample. since the sampling capacitors still hold the pre- vious sample, the analog inputs must supply a charge that is proportional to the change in voltage between the current sample and the previous sample. additionally there is a fixed charge associated with the turn-on of the nmos sampling switches. ideally, the input circuitry should be fast enough to fully charge the sampling capacitor during the sampling period 1/2f encode . however, this is not always possible and the incomplete settling may degrade the sfdr. the sampling glitch has been designed to be as linear as possible to minimize the effects of incomplete settling. ltc 2107 2107f for more information www.linear.com/ltc2107
18 applications information particular care has to be taken when driving the adc with test equipment involving long bnc cables. such a situation can create reflections in the bnc cable which will degrade sfdr. connecting a 3 db attenuator pad at the input to the demo board will help mitigate this problem. drive impedance as with all high performance, high speed adcs the dy - namic per formance of the ltc2107 can be influenced by the input drive circuitry, particularly the second and third harmonics. source impedance and input reactance can influence sfdr. at the falling edge of enc the sample and hold circuit will connect the 5.72 pf sampling capacitor to the input pin and start the sampling period. the sampling period ends when enc rises, holding the sampled input on the sampling capacitor. the analog input drive impedance will affect sampling bandwidth and settling time. the input impedance of the ltc2107 is primarily capacitive for frequencies below 1 ghz. higher source impedance will result in slower settling and lower sampling bandwidth. the sampling bandwidth is typically 800mhz with a source impedance of 25. better sfdr results from lower input impedance. for the best performance it is recommended to have a source impedence of 50 or less for each input. the source impedance should be matched for the differential inputs. poor matching will result in higher even order harmonics, especially the second. pga function the ltc2107 has a programmable gain amplifier sample/ hold circuit. the gain can be controlled through the serial or parallel modes of operation. pga = 0 selects a sample/hold gain of 1 and an input range of 2.4v p-p . pga = 1 selects a sample/hold gain of 1.5 and an input range of 1.6v p-p . the pga setting allows flexibility for adc drive optimization. a lower adc input signal eases the oip3 requirements of the adc driver circuit.the lower input range of the pga = 1 setting is easier to drive and has lower distortion for high frequency applications. for pga = 1, snr is lower by 2.3db as compared to pga = 0; however the input referred noise is improved by 1.2db. table 1. pga settings pga = 0 pga = 1 unit input range 2.4 1.6 v p-p snr, idle channel 80 77.7 dbfs input referred noise 85 74 v rms input drive circuits the inputs should be driven differentially around a com- mon mode voltage set by the v cm output pin, which is nominally 1.2 v. for the 2.4 v input range, the inputs should swing from v cm C 0.6 v to v cm + 0.6 v. there should be 180 phase difference between the inputs. v cm 2.2f 1.2v 1.8v 1.2v 0.6v 1.8v 1.2v common mode voltage set by v cm pin 1.2v 0.6v a in + a in + ltc2107 2107 f03 figure 3. input voltage swings for the 2.4v input range transformer coupled circuits rf transformers offer a simple, low noise, low power, and low distortion method for single-ended to differen - tial conversion, as well as voltage gain and impedance transformation. figure 4 shows the analog input being driven by a transmission line transformer and flux-coupled transformer combination circuit. the secondary coil of the flux-coupled transformer is biased with v cm , setting the a/d input at its optimal dc level. there is always a source impedance in front of the adc seen by its input pins a in + and a in C . source impedance greater than 50 can reduce the input bandwidth and increase high frequency distor- tion. a disadvantage of using a transformer is the signal loss at low frequencies. most small rf transformers have poor performance at frequencies below 1mhz. at higher input frequencies a single transmission line balun transformer is used (figures 5 to 6). ltc 2107 2107f for more information www.linear.com/ltc2107
19 figure 4. single-ended to differential conversion using tw o transformers. recommended for input frequencies from 5mhz to 100mhz applications information figure 5. single-ended to differential conversion using tw o transformers. recommended for input frequencies from 100mhz to 250mhz figure 6. single-ended to differential conversion using one transformer. recommended for input frequencies above 250mhz v cm a in + 2.2f 0.1f 10pf 0.1f wbc1-tlb 0.1f analog input 10 20 200 a in + 20 ltc2107 maba-007159 -000000 31.6 31.6 2107 f04 v cm a in + 2.2f 0.1f 10pf 0.1f 0.1f analog input 10 20 200 a in + 20 ltc2107 maba-007159 -000000 maba-007159 -000000 31.6 31.6 2107 f05 v cm a in + 2.2f 0.1f 4.7pf 0.1f 0.1f analog input 10 5 10 10 a in + 5 ltc2107 maba-007159 -000000 25 25 2107 f06 dither the dither function enhances the sfdr performance of the ltc2107. dither can be turned on by writing a 1 to register a1[2]. for brevity, the text will refer to a in + C a in C as a in . the dither function adds a pseudorandom dither voltage to the sampled analog input at the front of the adc, yielding a in + dither. this signal is converted by the adc, yielding a in + dither in digital format. dither is then subtracted, yielding the a in value at the output of the adc in 16 bit resolution. the dither function is invisible to the user. the input signal range of the adc is not affected when dither is turned on. reference the ltc2107 has an internal 1.25 v voltage reference. connecting sense to v dd or gnd selects use of the in- ternal 1.25 v reference. the sense pin is also the input for an external 1.25 v reference. figure 7 shows how an external 1.25 v reference voltage or the internal 1.25v reference can be used. figure 8 shows how an external 1.25v reference voltage can be configured. either internal or external reference will result in an adc input range of 2.4v p-p with pga = 0. ltc 2107 2107f for more information www.linear.com/ltc2107
20 applications information encode input the signal quality of the differential encode inputs strongly affects the a/d noise performance. the encode inputs should be treated as analog signalsdo not route them next to digital traces on the circuit board. sinusoidal, pecl , or lvds encode inputs can be used. the encode inputs are internally biased to 1.25 v through 5 k equivalent resistance. an optional 100 termination resistor can be figure 12. pecl or lvds encode drive figure 11. sinusoidal encode drive turned on by writing a 1 to control register bit a3[5]. the encode inputs can be taken up to v dd , and the common mode range is from 1.1v to 1.5v. for good jitter performance a high quality, low jitter clock source should be used. a 2v p-p differential encode signal is recommended for optimum snr performance. refer to figure 10 for clock source jitter requirements to achieve a desired snr at a given input frequency. figure 9. equivalent encode input circuit figure 10. ideal snr versus analog input frequency and clock source jitter 5k 5k enc + ltc2107 enc ? optional 100 termination 1.25v v dd differential comparator 1.25v 2107 f08 analog input frequency (mhz) 10 55 snr (dbfs) 60 65 70 75 85 100 1000 2107 f10 80 0fs rms 50fs rms 100fs rms 200fs rms additive jitter 24.9 24.9 2107 f11 0.1f 10 2v p-p 10 0.1f sinewave input maba-007159 -000000 bandpass filter (recommended for low noise applications) 0.1f lt2107 enc + enc ? 2v p-p 0.1f capacitors 0402 package size pecl or lvds clock enc ? 2107 f12 0.1f enc + ltc2107 figure 8. using an external 1.25 v reference. ltc2107 v cm sense 25k v dd lt1634-1.25 2.2f 0.1f 2107 f08 figure 7. reference circuit. internal adc reference tie sense to 0v or v dd to use the internal 1.25v reference tie sense to a 1.25v reference to use an external reference reference selection circuit 1.2v sense ltc2107 1.25v v cm buffer 2.2f 2107 f07 1.25v bandgap reference ltc 2107 2107f for more information www.linear.com/ltc2107
21 figure 13. functionality of keep-alive oscillator applications information clock duty cycle stabilizer the clock duty cycle stabilizer ( dcs) is a circuit that pro- duces a 50% duty cycle clock internal to the ltc2107 from a non 50% duty cycle encode input. the clock dcs is off by default and is enabled by writing a 1 to control register bit a 3[0] ( serial programming mode only). when the dcs is disabled optimum adc performance is achieved when the encode signal has a 50%(5%) duty cycle. when the optional clock duty cycle stabilizer circuit is enabled, the encode duty cycle can vary from 30% to 70% and the duty cycle stabilizer will maintain a constant 50% internal duty cycle. if the encode signal changes frequency or is turned off and on again, the duty cycle stabilizer circuit requires approximately one hundred clock cycles to lock onto the input clock and maintain a steady state. for applications where the sample rate needs to be changed quickly, the clock duty cycle stabilizer can be left disabled. if the duty cycle stabilizer is disabled, care should be taken to make the sampling clock have a 50%(5%) duty cycle. keep-alive oscillator there are many circuits on the ltc2107 which depend on the presence of a clock for refresh purposes, proper functionality and biasing. however an encode clock may not be available to the ltc2107 all of the time during operation. the keep- alive oscillator ensures the presence of an on- chip 800khz clock when an encode clock is not active at enc + / enc C . the keep-alive oscillator functionality is shown in figure 13. the purpose of this function is to enable fast operation of the adc when an encode clock does become active at the enc + /enc C pins. see the mid-scale and full- scale settling performance plots for evidence of fast adc recovery when the enc + /enc C clock becomes active. the keep-alive oscillator can be disabled by writing a 1 to a3[4]. in the event that the keep-alive oscillator is disabled and a clock is not active at the enc + /enc C pins there will be no on-chip clock active. this will also result in elevated input leakage current on the a in + /a in C pins. digital outputs digital output modes the ltc2107 can operate in two digital output modes: cmos mode or double data rate lvds mode. the output mode is set by mode control register a 4[0] ( serial pro - gramming mode), or by cs ( parallel programming mode). lvds mode is generally used to reduce digital noise on the printed circuit board. to adc core clkdet 2107 f13 enc + ltc2107 enc ? differential comparator clock detection circuit 800khz keep-alive oscillator ltc 2107 2107f for more information www.linear.com/ltc2107
22 applications information cmos mode in cmos mode the 16 digital outputs ( d0-d15), overflow (of), and the data output clocks (clkout + , clkout C ) have cmos output levels. the outputs are powered by ov dd and ognd which are isolated from the a/d core power and ground. for good performance the digital outputs should drive minimal capacitive loads. if the load capacitance is larger than 5pf a digital buffer should be used. cmos mode is not recommended for sampling rates greater that 100msps. double data rate lvds mode in double data rate lvds mode, two data bits are multi- plexed and output on each differential output pair. there are eight lvds adc data output pairs : (d0_1 + /d0_1 C through d 14_15 + /d 14_15 C ) . overflow ( of + / of C ) and the data output clock (clkout + /clkout C ) each have an lvds output pair. by default the outputs are standard lvds levels : 3.5ma output current and a 1.25 v output common mode volt- age. an external 100 differential termination resistor is required for each lvds output pair. the termination resistors should be located as close as possible to the lvds receiver. the outputs are powered by ov dd and ognd which are isolated from the a/d core power and ground. in lvds mode, ov dd should be 1.8v. programmable lvds output current in lvds mode, the default output driver current is 3.5ma. this current can be adjusted by serially programming mode control register a4. available current levels are 1.75ma, 2.1ma, 2.5ma, 3ma, 3.5ma, 4ma and 4.5ma. optional lvds driver internal termination in most cases using just an external 100 termination resistor will give excellent lvds signal integrity. in addi - tion, an optional internal 100 termination resistor can be enabled by serially programming mode control register a 4[3]. the internal termination helps absorb any reflections caused by imperfect termination at the receiver. when the internal termination is enabled, the output driver current is doubled to maintain the same output voltage swing. overflow bit the overflow output bit ( of) outputs a logic high when the analog input is either overranged or underranged. the overflow bit has the same pipeline latency as the data bits. in full-rate cmos mode of is the overflow pin. in ddr lvds mode of C /of + are the two differential overflow pins. sustained over-range or under-range beyond 120% of full-scale, for more than 20,000 samples may produce erroneous adc codes and an extended adc recovery time . phase shifting the output clock in full rate cmos mode the data output bits normally change at the same time as the falling edge of clkout + , so the rising edge of clkout + can be used to latch the output data. in double data rate lvds mode the data output bits normally change at the same time as the falling and rising edges of clkout + . to allow adequate setup and hold time when latching the data, the clkout + signal may need to be phase shifted relative to the data output bits. most fpgas have this featurethis is generally the best place to adjust the timing. the ltc2107 can also phase shift the clkout + /clkout C signals by serially programming mode control register a3[2:1]. the output clock can be shifted by 0, 45, 90, ltc 2107 2107f for more information www.linear.com/ltc2107
23 applications information or 135. to use the phase shifting feature the clock duty cycle stabilizer must be turned on. writing a 1 to a3[0] will invert the polarity of clkout + and clkout C , inde- pendently of the phase shift. the combination of these two features enables phase shifts of 45 up to 315 (figure 14). d ata format table 2 shows the relationship between the analog input voltage, the digital data output bits and the over-flow bit. by default the output data format is offset binary. the 2 s complement format can be selected by serially program - ming mode control register a5[0] phase shift 0 0 0 0 45 0 0 0 90 0 1 0 135 0 1 1 180 clkout + d0-d15, of enc + 1 0 0 225 1 0 1 270 1 1 0 315 2107 f14 1 1 1 clkinv clkphase1 mode control bits clkphase0 figure 14. phase shifting clkout table 2. output codes vs input voltage a in + C a in C (2.4v range) of d 15 C d0 (offset binar y) d15 C d0 (2s complement) >1.2000000v +1.1999634v +1.1999268v 1 0 0 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1110 0111 1111 1111 1111 0111 1111 1111 1111 0111 1111 1111 1110 +0.0000366 v +0.0000000v C0.0000366v C0.0000732v 0 0 0 0 1000 0000 0000 0001 1000 0000 0000 0000 0111 1111 1111 1111 0111 1111 1111 1110 0000 0000 0000 0001 0000 0000 0000 0000 1111 1111 1111 1111 1111 1111 1111 1110 C1.1999634 v C1.2000000v ?C1.200000v 0 0 1 0000 0000 0000 0001 0000 0000 0000 0000 0000 0000 0000 0000 1000 0000 0000 0001 1000 0000 0000 0000 1000 0000 0000 0000 ltc 2107 2107f for more information www.linear.com/ltc2107
24 applications information digital output randomizer interference from the a/d digital outputs is sometimes unavoidable. digital interference may be from capacitive or inductive coupling or coupling through the ground plane. even a tiny coupling factor can cause unwanted tones in the adc output spectrum. by randomizing the digital output before it is transmitted off chip, these unwanted tones can be randomized which reduces the unwanted tone amplitude. the digital output is randomized by applying an ex- clusive-or logic operation between the lsb and all other data output bits. to decode, the reverse operation is ap - pliedan exclusive-or operation is applied between the lsb and all other bits. the lsb, of and clkout outputs are not affected. the output randomizer is enabled by serially programming mode control register a5[1]. alternate bit polarity another feature that reduces digital feedback on the circuit board is the alternate bit polarity mode. when this mode is enabled, all of the odd bits ( d1, d3, d5, d7, d9, d11, d13, d15) are inverted before the output buffers. the even bits (d0, d2, d4, d6, d8, d10, d12, d14), of and clkout are not affected. this can reduce digital currents in the circuit board ground plane and reduce digital noise, particularly for ver y small analog input signals. when there is a very small signal at the input of the a/d that is centered around mid- scale, the digital outputs toggle between mostly 1 s and mostly 0 s. this simultaneous switching of most of the bits will cause large currents in the ground plane. by inverting every other bit, the alternate bit polarity mode makes half of the bits transition high while half of the bits transition low. to first order, this cancels current flow in the ground plane, reducing the digital noise. figure 15. functional equivalent of digital output randomizer figure 16. unrandomizing a randomized digital output signal d15 of d15 of clkout clkout ltc2107 d14 d14 d2 d2 d1 d0 2107 f15 d1 d0 randomizer on fpga clkout pc board of d15 d14 d2 d1 d0 2107 f16 ltc2107 ltc 2107 2107f for more information www.linear.com/ltc2107
25 applications information the digital output is decoded at the receiver by inverting the odd bits ( d1, d3, d5, d7, d9, d11, d13, d15). the alternate bit polarity mode is independent of the digital output randomizereither, both or neither function can be on at the same time. the alternate bit polarity mode is enabled by serially programming mode control register a5[2]. digital output test patterns to allow in-circuit testing of the digital interface to the a/d, there are several test modes that force the a/d data outputs (of, d15-d0) to known values: all 1s: all outputs are 1 all 0s: all outputs are 0 alternating: outputs change from all 1 s to all 0 s on alter - nating samples. checkerboard : outputs change from 10101010101010101 to 01010101010101010 on alternating samples. the digital output test patterns are enabled by serially pro - gramming mode control register a5[5:3]. when enabled, the test patterns override all other formatting modes : 2s complement, randomizer, alternate-bit-polarity. output disable the digital outputs may be disabled by serially program - ming mode control register a4[2]. all digital outputs in- cluding of and clkout are disabled. the high impedance disabled state is intended for long periods of inactivityit is too slow to multiplex a data bus between multiple con- verters at full speed. shutdown mode the a/d may be placed in shutdown mode to conserve power. in shutdown mode the entire a/d converter is powered down, resulting in 6.4 mw power consumption. shutdown mode is enabled by mode control register a1[1] (serial programming mode), or by shdn ( parallel or se - rial programming mode). the amount of time required to recover from shutdown is shown in the mid-scale settling performance plots. device programming modes the operating modes of the ltc2107 can be programmed by either a parallel interface or a simple serial interface. the serial interface has more flexibility and can program all available modes. the parallel interface is more limited and can only program some of the more commonly used modes. parallel programming mode to use the parallel programming mode, par / ser should be tied to v dd . the cs , sck, sdi, and shdn pins are binary logic inputs that set certain operating modes. these pins can be tied to v dd or ground, or driven by 1.8v, 2.5 v, or 3.3v cmos logic. table 3 shows the modes set by cs, sck, sdi and shdn. table 3. parallel programming mode control bits pin description cs digital output mode control bit 0 = full rate cmos digital output mode 1 = double data rate (ddr) lvds output modes sck programmable gain front-end (pga) control bit 0 = front-end gain = 1 (fs = 2.4v p-p ) 1 = front-end gain = 1.5 (fs = 1.6v p-p ) sdi digital output randomizer control bit 0 = digital output randomization disabled 1 = digital output randomization enabled shdn 0 = normal operation 1 = adc power shut down ltc 2107 2107f for more information www.linear.com/ltc2107
26 applications information serial programming mode to use the serial programming mode, par /ser should be tied to ground. the cs , sck, sdi and sdo pins become a serial interface that program the a/d mode control registers. data is written to a register with a 16- bit serial word. data can also be read back from a register to verify its contents. serial data transfer starts when cs is taken low. the data on the sdi pin is latched at the first 16 rising edges of sck. any sck rising edges after the first 16 are ignored. the data transfer ends when cs is taken high again. the first bit of the 16- bit input word is the r/w bit. the next seven bits are the address of the register (a6:a0). the final eight bits are the register data (d7:d0). if the r/ w bit is low, the serial data ( d7:d0) will be writ - ten to the register set by the address bits ( a6:a0). if the r/ w bit is high, data in the register set by the address bits (a6:a0) will be read back on the sdo pin ( see the timing diagrams). during a readback command the register is not updated and data on sdi is ignored. the sdo pin is an open-drain output that pulls to ground with a 260 impedance. if register data is read back through sdo, an external 2 k pull-up resistor is required. if se - rial data is only written and read back is not needed, then sdo can be left floating and no pull-up resistor is needed. table 4 shows a map of the mode control registers. software reset if serial programming is used, the mode control registers should be programmed as soon as possible after the power supplies turn on and are stable. the first serial command must be a software reset which will reset all register data bits to logic 0. to perform a software reset, bit a0[7] in the reset register is written with a logic 1. after the reset is complete, bit a0[7] is automatically set back to zero. all serial control bits are set to zero after a reset. grounding and bypassing the ltc2107 requires a printed circuit board with a clean unbroken ground plane. a multilayer board with an internal ground plane is recommended. layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. in particular, care should be taken not to run any digital track alongside an analog signal track or underneath the adc. high quality ceramic bypass capacitors should be used at the v dd , ov dd , and v cm pins. bypass capacitors must be located as close to the pins as possible. size 0402 ceramic capacitors are recommended for the 0.1f, 1f, 2.2f and 10 f decoupling capacitors. the traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. the analog inputs, encode signals, and digital outputs should not be routed next to each other. ground fill and grounded vias should be used as barriers to isolate these signals from each other. heat transfer most of the heat generated by the ltc2107 is transferred from the die through the bottom-side exposed pad and package leads onto the printed circuit board. for good electrical and thermal performance, the exposed pad must be soldered to a large grounded pad on the pc board. ltc 2107 2107f for more information www.linear.com/ltc2107
27 applications information table 4. serial programming mode register map register a0: reset register (address 00h) d7 d6 d5 d4 d3 d2 d1 d0 reset x x x x x x x bits 7 reset software reset bit 0 = not used 1 = software reset. all mode control registers are reset to 00h. this bit is automatically set back to zero after the reset is complete. the reset register is write only. bits 6-0 unused bits. read back as 0. register a1: adc control register (address 01h) d7 d6 d5 d4 d3 d2 d1 d0 x x x x pga dith shdn x bits 7-4,0 unused bits. read back as 0. bit 3 pga programmable gain front-end control bit 0 = front-end gain of 1. default value at start-up. 1 = front-end gain of 1.5 bit 2 dith dither control bit 0 = dither enabled. default value at start-up. 1 = dither disabled bit 1 shdn adc power shut down control bit 0 = normal operation. default value at start-up. 1 = adc power shut down ltc 2107 2107f for more information www.linear.com/ltc2107
28 register a2: not used (address 02h) d7 d6 d5 d4 d3 d2 d1 d0 x x x x x x x x bits 7-0 unused bits. read back as 0. register a3: clock control register (address 03h) d7 d6 d5 d4 d3 d2 d1 d0 x x encode term kaosc clkinv clkphase1 clkphase0 dcs bits 7-6 unused bits. read back as 0. bit 5 100 clock encode termination 0 = clock encode t ermination off. default value at start-up. 1 = clock encode t ermination on. bit 4 kaosc keep alive oscillator control bit 0 = keep alive oscillator enabled. default value at start-up. 1 = keep alive oscillator disabled. bit 3 clkinv output clock invert bit 0 = normal clkout polarity (as shown in the timing diagrams). default value at startup. 1 = inverted clkout polarity. bits 2-1 clkphase1:clkphase0 output clock phase delay bits 00 = no clkout delay (as shown in the timing diagrams). default value at start-up. 01 = clkout + /clkout C delayed by 45 (clock period 1/8) 10 = clkout + /clkout C delayed by 90 (clock period 1/4) 11 = clkout + /clkout C delayed by 135 (clock period 3/8) note: if the clkout phase delay feature is used, the clock duty cycle stabilizer must also be turned on. bit 0 dcs clock duty cycle stabilizer control bit 0 = clock duty cycle stabilizer off. default value at start-up. 1 = clock duty cycle stabilizer on. applications information ltc 2107 2107f for more information www.linear.com/ltc2107
29 register a4: output mode register (address 04h) d7 d6 d5 d4 d3 d2 d1 d0 x ilvds2 ilvds1 ilvds0 termon outoff x lvds bit 7 unused bit. read back as 0. bits 6-4 ilvds2:il vds0 lvds output current control bits 000 = 3.5ma l vds output driver current. default value at start-up. 001 = 4.0ma l vds output driver current. 010 = 4.5ma l vds output driver current. 011 = not used. 100 = 3.0ma l vds output driver current. 101 = 2.5ma l vds output driver current. 110 = 2.1ma l vds output driver current. 111 = 1.75ma l vds output driver current. bit 3 termon lvds internal t ermination bit 0 = internal t ermination off. default value at start-up. 1 = internal t ermination on. lvds output driver current is 2 the current set by ilvds2:ilvds0 bit 2 outoff output disable bit 0 = digital outputs are enabled. default value at start-up. 1 = digital outputs are disabled and have high output impedance. bit 1 unused bit. read back as 0. bit 0 lvds digital output mode control bit 0 = double data rate l vds output mode. default value at start-up. 1 = full-rate cmos output mode. applications information ltc 2107 2107f for more information www.linear.com/ltc2107
30 applications information register a5: d ata format register (address 05h) d7 d6 d5 d4 d3 d2 d1 d0 x x outtest2 outtest1 outtest0 abp rand twoscomp bits 7-6 unused bits. read back as 0. bits 5-3 outtest2:out test0 digital output t est pattern bits 000 = digital output t est patterns off. default value at start-up. 001 = all digital outputs = 0. 011 = all digital outputs = 1. 101 = checkerboard output pattern. of, d15-d0 alternate between 10101 0101 0101 0101 and 01010 1010 1010 1010. 111 = alternating output pattern. of, d15-d0 alternate between 00000 0000 0000 0000 and 11111 1111 1111 1111. note: other bit combinations are not used bit 2 abp alternate bit polarity mode control bit 0 = alternate bit polarity mode off. default value at start-up. 1 = alternate bit polarity mode on. bit 1 rand data output randomizer mode control bit 0 = data output randomizer mode off. default value at start-up. 1 = data output randomizer mode on. bits 0 twoscomp tw o s complement mode control bit 0 = offset binar y data format. default value at start-up. 1 = tw o s complement data format. ltc 2107 2107f for more information www.linear.com/ltc2107
31 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. 7.00 0.10 (4 sides) note: 1. drawing conforms to jedec package outline mo-220 variation (wkkd-2) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side, if present 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (see note 6) pin 1 chamfer c = 0.35 0.40 0.10 4847 1 2 bottom view?exposed pad 5.50 ref (4-sides) 0.75 0.05 r = 0.115 typ 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (uk48) qfn 0406 rev c recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 5.50 ref (4 sides) 6.10 0.05 7.50 0.05 0.25 0.05 0.50 bsc package outline 5.15 0.10 5.15 0.10 5.15 0.05 5.15 0.05 r = 0.10 typ uk package 48-lead plastic qfn (7mm 7mm) (reference ltc dwg # 05-08-1704 rev c) ltc 2107 2107f for more information www.linear.com/ltc2107
32 ? linear technology corporation 2014 lt 0414 ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltc2107 related parts typical application part number description comments high speed adcs ltc2208 16-bit 130msps, 3.3v adc 77.7db snr, 100db sfdr, 1250mw, cmos/lvds outputs, 9mm 9mm qfn-64 ltc 2209 16-bit 160msps, 3.3v adc 77.1db snr, 100db sfdr, 1530mw, cmos/l vds outputs, 9mm 9mm qfn-64 ltc2217 16-bit 105msps, 3.3v adc 81.6db snr, 100db sfdr, 1190mw, cmos/l vds outputs, 9mm 9mm qfn-64 ltc2195 16-bit 125msps, 1.8v dual adc, ultralow power 76.8db snr, 90db sfdr, 432mw, serial l vds outputs, 7mm 8mm qfn-52 ltc2271 16-bit 20msps, 1.8v dual adc, ultralow power 84.1db snr, 99db sfdr, 185mw, serial lvds outputs, 7mm 8mm qfn-52 fixed gain if amplifiers/adc drivers ltc6430-15 high linearity differential rf/if amplifier/adc driver 15db gain, +50dbm oip3, 3db nf at 240mhz, 5v/160ma supply baseband differential amplifiers ltc6409 1.1nv/hz single supply differential amplifier/adc driver 88db sfdr at 100mhz, ac- or dc-coupled inputs, 3mm 2mm qfn-10 rf mixers ltc5551 300mhz to 3.5ghz ultrahigh dynamic range mixer +36dbm iip3, 2.4db conversion gain, 0dbm lo drive, 670mw total power ltc2107 schematic (serial mode) sense gnd gnd v dd v dd v dd gnd a in + a in ? gnd v cm gnd 36 35 34 33 32 31 30 29 28 27 26 25 49 1 2 3 4 5 6 7 8 9 10 11 12 d12_13 + d12_13 ? d10_11 + d10_11 ? clkout + clkout ? d8_9 + d8_9 ? d6_7 + d6_7 ? d4_5 + d4_5 ? pad gnd enc + enc ? gnd shdn sdo ognd ov dd d0_1 ? d0_1 + d2_3 ? d2_3 + 48 47 46 45 44 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24 gnd gnd par/ ser cs sck sdi ognd ov dd of + of ? d14_15 + d14_15 ? ltc2107 1f 1f 2.2f 0.1f v dd 10f 1f sense a in + a in ? ov dd ov dd 2107 ta02 to controller or fpga digital outputs spi signals enc + enc ? ltc 2107 2107f for more information www.linear.com/ltc2107

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